Reducing Hardware in LUT-Based Mealy FSMs with Encoded Collections of Outputs

A method is proposed that focused on reducing the chip area occupied by logic elements creating circuit of Mealy finite state machines (FSMs). The aimed at FSM circuits implemented with internal resources field-programmable gate arrays (FPGA). required estimated number look-up table (LUT) in a particular circuit. based mutual application two methods structural decomposition. first them dividing set outputs and using unitary-maximum encoding collections outputs. second states classes compatible states. optimization achieved replacing maximum binary codes two-part this article. Each code consists class including inside class. approach leads to three-level LUT-based circuits. level generates three types partial functions: unitary encoded outputs, variables input memory functions. function represented single LUT. LUTs from generate final values these third implement An example synthesis applying discussed. experiments were conducted standard benchmark FSMs. Their results showed significant improving an LUT count decreased average 9.49%. positive side effect was increasing value operating frequency (on average, 8.73%). advisable use if single-level implementation impossible.